Introduction:
Integrated circuit design systems and test systems are closely related, in system implementation. Integrated circuit design is now routinely done utilizing computer programs that provide a design simulation environment that provides the circuit designer with a graphical user interface with which the designer enters data representing the logical relationships that the design is intended to implement. In response to such data, the program determines an efficient assemblage of semiconductor devices, in accordance with the process technology and logic circuit library with which the design simulation environment is used, and models various parameters of this resulting circuit. These parameters include signals at various points in the resulting circuit, including output ports, that arise as a result of a given stimulus of input signal or signals, and the relative timings thereof.
In turn, the circuit data and parameter data from the design system are used in related test systems to generate a sequence of data values for input at one or more input ports and to generate an expected sequence of data values at one or more output ports for a properly operating circuit. These related input and output test data are sometimes referred to as test vectors.
The tools just described greatly facilitate and shorten the time necessary to design circuits for integrated circuit fabrication, and the time to test the circuit so fabricated. However, even with these highly sophisticated tools, nonetheless integrated circuit designers still contend with various problems in integrated circuit test. For example, integrated circuit test engineers and designers must contend with the problems created by variations in signal paths, or delay paths, throughout a device.
As system clock frequency increases and the design grows in complexity, not only do absolute delays through the circuit in the various delay paths grow, but their magnitude relative to the system clock period increases as well. Consequently, variations in fabrication process, voltage and temperature can often produce changes greater than 400% on a given delay path. Nonetheless, while seemingly large, variations of this magnitude can be completely acceptable in many applications and are easily comprehended in the simulation environment. However, beyond the simulation environment, these delay variations greatly reduce the testability of high speed designs.
One reason for this is that prior art vector generation and test tools utilize a fixed timing reference point, i.e., clock-in or clock-out, with which to reference a timing reference window in which an output port is monitored for an expected signal during test. When using only a fixed timing reference point, it is not possible to compensate for delay variations that are large with respect to the reference window. For example, if the delay variations are large enough, the testability is reduced or completely lost when signals cross over reference boundaries between minimum, or rain, and maximum, or max, conditions.
FIG. 1 is a signal timing diagram showing an example of lost test coverage using a fixed reference window, based on a dock-in reference point. The fixed reference window in this example is based on the clock-in signal, CLKIN, which is a clock signal, or dock, applied to an input pin of the integrated circuit. The output being examined, CLKOUT, is a clock appearing on an output pin of the integrated circuit that is a function of both the low-high transition and the high-low transition on CLKIN as well as some variable delay path through the device. The CLKOUT signal is shown for both rain and max delay path conditions. The region between lines 10 and 12 represents the overlap of CLKOUT, from rain to max conditions. From FIG. 1, we can see that CLKOUT is unrestable at any point in the region between lines 10 and 12 due to the ambiguity between the rain and max values on this signal.
Clock-In Based Testing:
The standard approach to vector generation and testing is the fixed reference method discussed above. One version of this method, commonly referred to as clock-in based testing, simply requires an input clock to be the standard reference point in vector generation and testing. This fixed reference method, illustrated above in connection with FIG. 1, works well on slower synchronous designs; but, as previously discussed, this method is limited as the device frequency increases and the design grows in complexity.
Clock-Out Based Testing:
An alternative to clock-in based testing is clock-out based testing. Clock-out based testing uses the same fixed reference principle as clock-in based testing. However, in this second method the clock-out signal is used as the standard reference point. It is up to the test engineers or designers to derive techniques for synchronizing the test equipment with the clock-out signal of the device. Once synchronized, then the test patterns can be run with the clock-out based timing information. This method works well for devices which only need the clock-out reference, but cannot be used to test devices which also require signal timings with respect to a clock-in or other timing reference. Similar to the clock-in approach, this clock-out method cannot handle the high-speed or embedded devices which require multiple timing references.
Alternative Approach:
Another approach has been proposed that can also handle the rain to max delay variations that negatively effect testability. This other approach is to simply use two sets of test vectors for both min and max conditions. Set one of these vectors is used only under minimum voltage/temperature/process (VTP) conditions; while set two is used only under maximum VTP conditions. This two pattern approach helps to improve testability, but has several obvious implementation and test time disadvantages.
The first problem with the two set method is the discrepancies in controllable parameters between the simulation and the test environment. Simulations are run with specified values of voltage, temperature and process parameters. While testing is done only under control of voltage and temperature, the process parameters on a real device are fixed during fabrication within an allowable minimum to maximum range, and cannot be modified when testing the device. Acknowledging this difference, two simulations have to be done at each fixed voltage and temperature under both min and max process conditions. The two separate simulations then have to be used for vector generation which is only valid at the given voltage and temperature. Using this method requires doubling the needed number of simulations at each voltage and temperature. Aside from doubling the number of simulations, the second problem is that this approach also doubles the number of patterns needed to test the device. The resultant simulation and test time impact of this approach makes it impractical.
The present invention overcomes these problems, and provides a method for testing an integrated circuit that provides testability of integrated circuits over significantly greater delay path variations than allowed by prior art test systems. In addition, the present invention provides improved testability for integrated circuits in which integrated circuit types having traditionally differing test methodologies are combined.